DN-YOLOv5的金属双极板表面缺陷检测算法

为解决氢燃料电池中金属双极板表面缺陷尺寸小，缺陷对比不明显、种类多造成的难以检测，易误检漏检以及缺陷检测模型复杂度太大难以部署等问题，提出一种改进版的金属双极板缺陷检测算法DN-YOLOv5,来探究缺陷检测在冲压成形的金属双极板视觉检测工作台场景下进行快速精准检测的可行性，从而实现智能检测，提升检测效率。本研究着重于修改YOLOv5主干网络Backbone部分，添加网络中模块数量，加入NAM注意力机制和使用深度可分离卷积模块来替代原来CSP/CBS主干网络卷积模块，并引入SIoU对损失函数重新进行了定义，极大的提升了主干网络的轻量化程度。结果表明，本算法的map@0.5可达0.988,每秒检测传输帧率为9.98,模型参数量降低了52.13%,在测试集75张缺陷图像中真检率达到了99.74%。该方法在保证模型较高检测率的同时，显著降低了模型复杂度和参数计算量。此外，该算法结合新的检测尺度设计特征融合网络，提升网络的小目标、多目标检测能力。该算法具有良好的稳定性和鲁棒性，综合性能较好，满足部署移动端场景进行缺陷检测的轻量化需求。     

Side-group engineering: The influence of norbornadienyl substituents on the properties of ethynylated pentacene and tetraazapentacene

The chemical modifications of 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-PEN) and 6,13-bis(triisopropylsilylethynyl)-5,7,12,14-tetraazapentacene (TIPS-TAP) by introduction of a large norbornadienyl substituent at the silyl atom of the side chain were examined and their effect on the charge transport properties in organic field-effect transistors (OFETs) was investigated. While the introduction of the norbornadienyl substituent resulted in only small changes in the crystallographic packing of these materials and did not affect the optical and electronic properties, the effect on the charge carrier mobility is significant. The hole mobility for the norbornadienyl substituted pentacene (Nor-PEN) is increased compared to similarly prepared TIPS-PEN devices, reaching up to 0.75 cm²/Vs. On the other hand, the electron mobility of the tetraaza derivative (Nor-TAP) is reduced by an order of magnitude compared to its parent TIPS-TAP. The strong effect of the norbornadienyl substitution on the charge carrier mobilities can be explained by the calculation of the transfer integrals and the microstructure of the resulting films of the Nor-derivatives.     

SQM-OTFT: A compact model of organic thin-film transistors based on the symmetric quadrature of the accumulation charge considering both deep and tail states

A physically-based compact model of organic thin-film transistors suitable for CAD simulators is proposed. It is worked out by means of a newly developed and particularly simple form of the charge-sheet model: the symmetric quadrature of the accumulation charge. The model is based on the variable-range hopping and accounts for both deep and tail states. It is simple, symmetric, accurately accounts for the below-threshold, linear, and saturation regimes via a unique formulation. The symmetric quadrature is accurate within 5% in all regions of operation and the resulting current model is suitable both for p- and n-type transistors. The model leads to a significant simplification of the drain current and of the quasi-static expressions of the terminal charges based on the Ward–Dutton partition. Finally, the symmetric quadrature leads to an explicit and analytically tractable solution for the surface potential as a function of position in the device channel that can be extremely useful to implement advanced physical effects.     

Role of geometry, substrate and atmosphere on performance of OFETs based on TTF derivatives

We report a comparative study of OFET devices based on zone-cast layers of three tetrathiafulvalene (TTF) derivatives in three configurations of electrodes in order to determine the best performing geometry. The first testing experiments were performed using SiO₂/Si substrates. Then the optimum geometry was employed for the preparation of flexible OFETs using Parylene C as both substrate and dielectric layer yielding, in the best case, to devices with μ_FET = 0.1 cm²/V s. With the performed bending tests we determined the limit of curvature radius for which the performance of the OFETs is not deteriorated irreversibly. The investigated OFETs are sensitive to ambient atmosphere, showing reversible increase of the source to drain current upon exposition to air, what can be explained as doping of TTF derivative by oxygen or moisture.     

Effect of reactive sputtered SiOx passivation layer on the stability of InGaZnO thin film transistors

We fabricated the indium-gallium-zinc oxide (IGZO) thin film transistor (TFT) with reactive sputtered SiO_x as passivation layer, and investigated the role of the SiO_x passivation layer in the IGZO-TFT under gate bias stress. The bias stability of IGZO-TFT with passivation layer is much better than that of IGZO-TFT without passivation layer. After applying positive bias stress of 20 V for 10000s, the device without passivation layer shows a larger positive V_th shift of 7.3 V. However, the device with passivation layer exhibits a much smaller V_th shift of 1.3 V. It suggests that V_th instability is attributed to the interaction between the exposed IGZO back surface and oxygen in ambient atmosphere during the positive gate voltage stress. The results indicate that reactive sputtered SiO_x passivation layer can effectively improve the bias stability of IGZO-TFT.     

Crosslinked polymer-mixture gate insulator for high-performance organic thin-film transistors

In this paper, we report on the fabrication of a crosslinked polymer-mixture gate insulator for high-performance organic thin-film transistors (TFTs). We used cyanoethylated pullulan (CEP) as a crosslinkable high-k polymer matrix and poly(ethylene-alt-maleic anhydride) (PEMA) as a polymeric crosslinking agent. Because PEMA has a high number of functional groups reactive to the hydroxyl groups of CEP, the use of PEMA is effective for minimizing the amount of remaining hydroxyl groups strongly related to the large current hysteresis and high off current of the organic TFTs. To investigate the potential of the CEP-PEMA mixture as a gate insulator, we fabricated 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C₈-BTBT) TFTs. The C₈-BTBT TFT with the 60 nm-thick CEP-PEMA gate insulator showed excellent TFT performance with a field-effect mobility of 1.4 cm²/V s and an on/off ratio of 2.4 × 10⁶.     

基于硅衬底静电感应晶体管器件仿真与研究

针对静电感应晶体管理论研究迟滞于实践过程,文中利用软件Silvaco Tcad,从器件仿真入手,对影响硅基表面栅静电感应晶体管器件电学性能进行了理论研究。仿真得到了反偏栅压约为0 V、漏电压＜20 V时,器件表现类五极管饱和特性曲线,器件电流约为10-5 A,此时沟道状态为预夹断。当反偏栅压为-1.5 V、漏电压逐渐增大到300 V时,器件表现为类三极管不饱和特性曲线,器件电流约为10-6 A,此时沟道状态为完全夹断,研究结果静电感应晶体管工艺实践提供了参考。